Project brief
From scenario and baseline to reproducible evidence.
Map a trained, fixed-weight neural network to dedicated inference hardware and measure the trade-offs in area, latency, throughput, and energy.
The handbook starts with a runnable minimum, then adds real constraints. The final presentation should explain the method, results, failures, limitations, and next steps.
Evaluation focus
Use metrics to make trade-offs visible.
Project handbook
Project brief
Choose a small public model with a clear license, such as an MNIST or CIFAR classifier, keyword spotter, or anomaly detector. Compare programmable weight storage with a version where some or all quantized weights become RTL constants, lookup tables, or synthesis-time constants.
Minimum version
Reproduce the model accuracy on a CPU, write a fixed-point reference, and implement at least one layer in Verilog, SystemVerilog, HLS, or an equivalent hardware flow.
- Compare FP32, INT8, or lower-bit precision.
- Use Verilator or iverilog for functional simulation.
- Report resource use, cycles, timing, and an energy estimate with assumptions.
- Test software and hardware outputs for consistency.
Evaluation and boundaries
Simulation, synthesis, or an FPGA demo is sufficient; do not claim the result is a taped-out chip. Do not use restricted PDKs, confidential weights, or unlicensed commercial IP.
Resource note: External code, models, datasets, and platforms remain subject to their own licenses, terms of service, and applicable law.